How an independent architect in Kocaeli, Turkey, set out to move the first decision of every always-on system into hardware, what it took to prove it, and why open source made it possible.
Here is something every hardware engineer knows and almost nobody says directly: a processor cannot decide to go to sleep without first being awake to make that decision. It wakes up, checks whether anything has changed, finds that nothing has, and goes back to sleep. Then it does it again. For data that has not moved.
This is not a bug. It is a structural property of how computers work: the processor sits inside the loop that is supposed to manage the processor. The industry built increasingly careful tools around it, such as DVFS, power-management units, interrupt comparators and smart sensors. Each one helps. None of them moves the first decision, "is this worth waking for?", out of the processor's hands.
We called it the stagnation tax: power and attention spent only to confirm that nothing has changed. In an implant it drains the battery and warms the tissue. In a sensor network it decides how often batteries are changed. In a safety system it ties a trigger to firmware that can hang.
Serious research groups have explored change-driven, adaptive sensing. IBM built neuromorphic architectures that adapt at the network level. HP pursued memristors, devices that hold the memory of past stimuli in their resistance. In 2024 researchers at Cambridge, Beihang University and UCL published a memristor-based adaptive perception system in Nature Communications. It is serious, well-executed science.
Those routes rely on new devices, specialised fabrication or a controller coordinating the adaptation. We were looking for something narrower and more immediately usable: a block in standard CMOS, synthesizable on any foundry node, that takes the first decision itself, before any computation starts.
The first working version was an FPGA prototype. A single light sensor fed the same data stream into two circuits on a Nexys A7 board: one conventional, always active whatever the sensor saw, and one gated by the RPU, dark until the light actually changed. You could watch the difference in real time.
We showed it to people who understood hardware. A professor whose research touched adjacent problems looked at it carefully, asked good questions, and used the word we would hear many times in the months that followed.
It was clarifying. The world does not move on interesting. It moves on evidence: synthesis results on a real process, a real processor integration, and tests that a sceptical engineer can repeat. An FPGA demonstration shows behaviour. It does not show that the design closes timing on a foundry process or behaves inside a real system.
For an independent architect without institutional affiliation, foundry relationships or a team, the conventional path to that evidence was not open.
The lowRISC Ibex core is an open-source RISC-V processor: clean, well documented, production quality, and maintained by lowRISC C.I.C. and its community. It exists because people believed processor design should not be locked behind institutional access. That belief mattered directly to us.
We built a system around the Ibex core, with memory, interconnect, timer and the RPU wired to the processor's external interrupt. The CPU sleeps in WFI and the RPU decides when to wake it. Early simulations against a busy polling loop showed the CPU's active cycles collapsing on a quiet signal. That comparison was the easy one, and we soon moved past it.
We synthesized the RTL in TSMC 65nm GP with Cadence Genus: timing met at 625 MHz, 2,960 standard cells. The same file synthesized in SkyWater SKY130, the open-source process, and met timing there too. The block is not tied to one node.
Without Ibex, none of this would exist. The open RISC-V ecosystem created the conditions under which one independent architect could produce evidence the semiconductor industry takes seriously.
The easy comparison flatters any idea. So we set out to break ours. The question we asked was blunt: against the cheapest thing that could do the same job, a well-tuned comparator, does the RPU earn its place?
We gave both sides equal tuning rights: settings chosen on one recording, frozen, then measured once on recordings neither had seen. A comparator can be tuned to look good on any one recording; the question is what happens when conditions change and nobody retunes it. Frozen and left alone, the RPU kept working: tuned once at one noise level, it caught every event across a rising noise sweep and, at the highest noise, woke the CPU about half as often as a comparator tuned the same way.
That result changed how we describe the RPU. It is a comparator of a new kind: a rate-of-change comparator with memory. Memory is what lets it ignore drift, attenuate spikes, follow the noise floor, and notice things a comparator never can, such as a sensor that has frozen or a detector that has lost sensitivity. And because it is a building block, everything that engineers build around a comparator can be built around it as shells, without touching the core.
So we built them. An event shell now coalesces interrupts, caps the event rate and reports a stopped stream, a lost heartbeat or a frozen value on a separate fault line. Each was added without changing a byte of the verified core, and the current system kit passed 101 of 101 board runs matching full-system simulation. Then we ran real recordings through a model that matches the RTL bit for bit: on real earthquake records it detected P-wave arrivals on par with STA/LTA, 213 against 210 of 300, at every false-alarm budget we tested, and with a simple rectifier in front it caught 25 of 27 bearing faults with no false alarms; two RPU cells, one on the raw signal and one on its envelope, caught all 27. Testing at the real sample rate later exposed a flaw of our own: the wake budget raised a fault interrupt for every alarm it suppressed. We fixed it, rebuilt every bitstream and repeated all 101 board runs; on the same seismic data the CPU was woken 315 times instead of 798, with the same events delivered.
In September 2025 we filed the Turkish priority application, TR 2025/012696. The search report issued by TÜRKPATENT cites four documents: Wang et al. (Nature Communications, 2024) and an HP memristor patent in category Y, and an IBM neuromorphic patent and a University of Michigan patent in category A. On 27 March 2026 we filed the international application, PCT/IB2026/053070. It is pending.
By April 2026 RPU Microelectronics was formally registered and the RPU was listed on Design & Reuse, where semiconductor IP is evaluated by the engineers who build chips. Within the first week the editorial team selected it as Product of the Week. Engineers from Texas Instruments, Marvell, Silicon Labs, Synopsys, Socionext, IDEMIA, Alphawave, Agile Analog, Viettel's semiconductor division, and universities in the United States, Australia, Vietnam, Germany, France and the United Kingdom visited the listing.
We are grateful to the Design & Reuse team, and particularly to Gabriela, for believing in the work and giving it that visibility.
We have not signed a licence yet. We are a new company with a new architecture, in an industry that rightly moves carefully on both. We designed the RPU for that: a side-band block with a small, reversible integration and two evaluation kits that let a team check our numbers on a board before trusting them.
This work was possible because people chose to build open infrastructure and make it available to everyone. lowRISC built and maintains Ibex. The SkyWater SKY130 PDK exists because of a deliberate decision to open a process node. Yosys, Icarus Verilog and Verilator exist because their authors chose to share them. Each lowered a barrier that would otherwise have stopped us.
Our response is concrete. Reference RTL and testbenches are published on GitHub, and research and academic use is free. Commercial use, meaning SoC integration, tape-out and products, requires a written licence. We consider it a debt, and we intend to pay it.
The next steps are plain: pilots on customer sensor data, field tests with a live ADC, and a tape-out partner. Licensing details are on a separate page: What We License →
The foundation for hardware that senses the rate of change of the world around it, rather than simply executing instructions about it, has been laid. We do not know everything that will be built on it. We know the door is open, and that it was worth keeping open.