The Missing
Reflex

Here is something that every hardware engineer knows and almost nobody says directly: a processor cannot decide to go to sleep without first being awake to make that decision. It wakes up, checks whether anything has changed, finds that nothing has, and goes back to sleep. Then it wakes up again. Millions of times per second. For data that has not moved.

This is not a bug. It is not a design flaw that someone forgot to fix. It is a structural property of how computers work — the processor sits in the loop that is supposed to manage the processor. The industry gave it a polite name, power management, and built increasingly sophisticated software around it: DVFS, PMUs, interrupt comparators, smart sensors. Each one helped at the margins. None of them broke the loop.

We called it the Von Neumann Stagnation Tax. Every cycle spent confirming that nothing changed is a cycle taxed from the system for no return. In a medical implant, that tax drains the battery. In a data centre, it runs into terawatt-hours annually. In an autonomous vehicle, it consumes compute headroom that safety systems need. The tax is universal, and until recently, it was considered unavoidable.

IBM sent serious researchers at this problem and built neuromorphic architectures that could adapt at the network level. The science was real. But they still needed an external controller — a conventional instruction loop running somewhere — to coordinate the adaptation. The loop was smaller. It was not gone.

HP tried memristors: passive resistance-switching devices that could hold state without power. The concept was elegant. The materials were not. Memristors do not exist in standard foundry libraries. They require specialised fabrication that lives inside a handful of laboratories in the world.

In 2024, a collaboration between researchers at Cambridge, Beihang University, and UCL published a memristor-based neuromorphic perception system in Nature Communications. It was serious, well-executed science involving some of the best minds working on this problem. It required a memristor array fabricated at a specialised facility.

None of these approaches reached the thing we were looking for: a standard CMOS block, synthesisable on any foundry node, that removes the processor from the decision loop entirely — not manages it better, not approximates it in software, but removes it.

The first working version was an FPGA prototype. A single LDR sensor fed the same data stream into two circuits running in parallel on a N​exys​ A7 board — one conventional, always drawing power regardless of what the sensor saw. One RPU-gated, completely dark until the light level actually changed. You could watch the difference in real time. The logic was correct. The behaviour matched the theory exactly.

We showed it to people who understood hardware. A professor whose research touched adjacent problems looked at it carefully, asked good questions, and used the word we would hear many times in the months that followed.

We sat with that for a while. It was not discouraging, exactly — it was clarifying. The world does not move on interesting. It moves on proof, and proof in semiconductor architecture means one thing: silicon. Measured results. Timing closure reports. A real processor integration with real cycle counts from a real simulation.

An FPGA prototype demonstrates behaviour. It does not prove that the architecture survives synthesis at production frequencies, that it closes timing on a real process node, that it integrates cleanly into a production SoC environment. Without that evidence, interesting stays interesting. It does not become a product.

We needed silicon-grade validation. And for an independent architect without institutional affiliation, without foundry relationships, without a team — the conventional path to that validation was not open.

The lowRISC I​bex core is an open-source RISC-V processor — clean architecture, well-documented, production-quality, actively maintained by l​owRISC C.I.C. and the open-source community around it. It exists because people believed that processor design should not be locked behind institutional access. That belief turned out to matter directly to us.

We built a complete SoC testbench around the I​bex RV32IMC core: memory, bus interconnect, timer, and the RPU connected directly to the processor's external interrupt input. We ran three workload scenarios over five million simulation cycles using V​erilator. Stable sensor data with noise. A sudden spike. A slow drift followed by a large anomaly. In every scenario, the RPU held the processor in sleep until a real event occurred, woke it in exactly two clock cycles, and produced zero false wake-ups and zero missed events.

On stable data — the condition that characterises the vast majority of always-on systems — the RPU reduced active CPU cycles by 99.998%. Five million cycles became 125.

We then synthesised the RTL on TSMC 65nm GP using C​adence G​enus. 625 MHz. Zero timing violations. 2,960 standard gates. 1.70 milliwatts average power. Full timing closure. The same file synthesised on S​kyWater S​KY130 — the open-source process node — and closed timing there as well. The architecture was node-agnostic. It would synthesise on any standard CMOS process.

Without I​bex, none of this evidence existed. That is not a formality. It is a physical fact about how the validation was produced. The open-source RISC-V ecosystem created the conditions under which a single independent architect, working without institutional backing, could generate the kind of results that the semiconductor industry recognises as credible. The barrier of access — the one that stopped the work before it started — was removed because the community chose to remove it.

The T​ÜRKPATENT international search report arrived in December 2025. We knew what it would contain — we had done our own analysis — but reading a formal legal determination is different from doing your own analysis. The examiner had searched the complete prior art landscape and identified the three closest references: Wang et al. from Nature Communications 2024, HP's memristor patent from 2013, IBM's neuromorphic architecture patent from 2021.

Wang et al. and HP received Y-category codes — closest prior art, considered in combination. IBM received an A-category code — relevant background, not considered directly blocking. No single reference anticipated the architecture. Novelty and inventive step were not contradicted by any prior art found.

IBM. HP. A team from Cambridge and Beihang and UCL. The patent authority compared our work directly against all of them and found it new. That determination is not ours — it belongs to the examiner, to the process, to the record. It is on file and publicly verifiable.

The PCT international application — P​CT/IB2026/053070 — was filed on 27 March 2026, covering 153 WIPO member countries.

By April 2026 — eight months after the patent application, five months after the FPGA prototype — R​PU Microelectronics was formally registered. The RPU was listed on D​esign & Reuse, the platform where semiconductor IP is evaluated by the engineers who actually build chips. Within the first week, the editorial team selected it as Product of the Week.

What happened in the following hours is worth describing plainly. Engineers from Texas Instruments, Marvell, Silicon Labs, Synopsys, Socionext, IDEMIA, Alphawave, Agile Analog, Viettel's semiconductor division, and universities across the United States, Australia, Vietnam, Germany, France, and the United Kingdom visited the listing. Over a thousand click-throughs in the first days. The technology reached 36,000 semiconductor engineers through the platform.

We are grateful to the D​esign & Reuse team — and particularly to Gabriela — for believing in the work and giving it that visibility. That kind of recognition, from people who see hundreds of IP blocks every year, was not something we took for granted.

We have not signed a contract yet. We are a new company with a new architecture, and this is not an industry that moves quickly on either of those things. We knew that going in. We designed the RPU specifically for it — a parallel sideband block, zero integration risk, zero redesign of the host system. We did not ask anyone to bet their tape-out on an unknown. We asked them to add two wires and run their own benchmarks. The conversations that started in April are still ongoing.

Every document behind those results is publicly available. The ASIC PPA reports, the RISC-V benchmark data, the T​ÜRKPATENT search report, the system schematic — all downloadable from rpu​-micro.com. The RTL source, simulation testbench, and post-synthesis testbench with SDF annotation are on G​itHub. Nothing is behind a wall. Every claim we make can be independently verified.

We want to say something plainly, because it is true and because it matters. This work was possible because a community of people chose to build open infrastructure and make it available to everyone. l​owRISC built and maintains I​bex. The S​kyWater S​KY130 PDK exists because of a deliberate decision to open a process node. V​erilator exists because its authors chose to share it. Each of these things lowered a barrier that would otherwise have stopped us.

Our response is concrete. The RPU RTL is published on G​itHub. Any researcher, any student, any independent engineer who wants to build on this work or verify its results can do so without asking permission. Research and academic use is free. Commercial use — SoC integration, tape-out, and product deployment — requires a written commercial licence. The proof is reproducible — every number we have published can be arrived at independently by anyone with the right tools. We chose to open this work not because we had to. We chose it because the infrastructure that made our work possible was built by people who made the same choice before us. We consider it a debt, and we intend to pay it.

The full details of our patent, claim structure, and licensing model are on a separate page: What We License →

The seed of a solution to computing's energy problem has been planted in hardware. The foundations for hardware that senses the rate of change of the world around it — rather than simply executing instructions about it — have been established. We do not know exactly what gets built on those foundations. We know that the door is open. And we know — because we walked through it ourselves — that it was worth keeping open.