RPU Microelectronics · IP Licensing

What We License
and What It Protects

Every processor in the world is burning energy right now confirming that data has not changed.
The RPU stops this at the gate level. That is what this patent application protects.

We are a hardware IP company. We license one patent-pending architectural primitive that stops processors from wasting energy on data that has not changed — without touching anything else in your system.

PCT/IB2026/053070 153 WIPO countries Novel over IBM · HP · Wang Priority: TR 2025/012696 · 4 September 2025 Filed: 27 March 2026
I One company. One principle. One mission.

RPU Microelectronics is an IP licensing company. We do not build general-purpose chips. We do not sell processor cores. We license architectural primitives built on a single foundational principle: autonomous hardware decision-making driven by the temporal rate of change of data — ΔC/Δt.

Our first licensed product is the RPU — a patent-pending hardware IP block, silicon-proven on TSMC 65nm and SkyWater SKY130, and immediately deployable in any SoC. The RPU solves a problem every processor in the world shares: it cannot know whether incoming data has changed without waking up to check. The RPU replaces that check with a hardware decision made in one clock cycle, without software, without firmware changes, without touching your existing IP.

The patent application covers far more than this implementation. Every derivative, every topology, every process node that uses ΔC/Δt-based autonomous gating — regardless of HDL or application domain — falls within the scope of PCT/IB2026/053070. The RPU is the first product. It will not be the last.

Not just a file. A principle.
Patent pending · PCT/IB2026/053070 · 153 WIPO countries.
Invisible to your system — except when it matters.
II What changes. What does not.

The most common question we hear from integration engineers is: will this force us to redesign our system? The answer is no. The RPU is a sideband block — it connects in parallel to your existing data path and interrupt controller. It does not sit between your sensor and your processor.

Here is exactly what changes and what does not when you integrate the RPU:

What changes
When your processor wakes — only on genuine data change, in exactly 2 clock cycles
How much energy burns while waiting — near zero instead of full polling rate
Toggle rate on your clock tree — reduced by 15× on FPGA, proportionally on ASIC
What does not change
Your ISR and firmware logic
Your sensor interface and data path
Your existing IP blocks
Your bus topology and interconnect
Your application software

The RPU connects to two input signals and drives one output. That output connects to your interrupt controller — the same line your software already handles. Remove the RPU and your system returns to conventional polling with zero code changes and zero data loss.

III The technology — and what it is not limited to

The RPU as shipped — rpu_core.sv, 560 lines, synthesizable SystemVerilog — is the first commercial implementation of a broader architectural principle: using the temporal rate of change of data (ΔC/Δt) as the primary signal for autonomous hardware gating decisions.

The current implementation targets clock and power gating for processor wake-up. That is the problem we solved first because it is the most universal. But the principle applies anywhere a hardware system needs to decide, without software involvement, whether something meaningful has happened in a data stream.

The patent application covers the principle, not just this implementation. Any hardware that uses ΔC/Δt-based autonomous gating — regardless of HDL, process node, topology, or application domain — falls within the scope of pending PCT/IB2026/053070.

Reimplementing the same concept in a different HDL, different topology, or different process node does not circumvent this patent application. The concept is covered, not just the code.

The ΔC/Δt principle is not an engineering trick. It is a formalisation of how autonomous systems — from biological reflexes to physical state transitions — decide whether something meaningful has happened. The same threshold rule governs how a neuron fires, how a cell responds to a chemical gradient, how a physical system transitions between states. The RPU is the first implementation of this principle at the semiconductor level, in synthesisable standard CMOS. PCT/IB2026/053070 protects that implementation. Designing around it requires either abandoning the principle entirely or finding a different physical basis for autonomous gating that has never existed in prior art. Nobody has found one. The search report confirms it.

IV What the patent covers

The patent application is structured in three independent claim layers. To design around it, all three must be avoided simultaneously.

Claim Set A · Claim 1 — Principle level
Any hardware using ΔC/Δt for autonomous gating
Any semiconductor circuit that computes the temporal rate of change of its input or internal state and uses that computation to autonomously gate clock or power — without an external processor, software instruction cycle, or centralized control unit — falls within this claim.
Claim Set B · Claim 2 — Structural level
Any hardware decision chain with the same structure
Any hardware that operates on the same data path — from temporal analysis to physical effect — within a single autonomous structure, without requiring external coordination, falls within this claim regardless of the specific topology used.
Claim Set C · Claim 3 — Implementation level
The ring buffer + bit-shift + adaptive threshold architecture
The specific implementation: circular ring buffer, subgroup averaging via bit-shift, adaptive threshold with asymmetric step logic, connected to an ICG cell or sleep transistor — silicon-proven on TSMC 65nm and SkyWater SKY130.
Claim 10 The Strongest Claim
Direct causal path — no intermediate layer
Between the decision signal and the hardware effect, no intermediate processing, control logic, state machine, or functional decision layer exists. The decision is the effect. This claim has no prior art equivalent in the search report and is the hardest to design around.
V The prior art — what the patent office found

The TÜRKPATENT international search report formally compared the RPU against the most relevant prior art in this space. The examiner searched across IBM, HP, and the most recent academic work in neuromorphic and memristor-based approaches.

Reference Year Approach Result
Wang et al.
Nature Communications · Cambridge, Beihang, UCL		 2024 Memristor-based neuromorphic perception. Specialised fabrication. Not synthesisable on standard CMOS. Y-code · novel
HP · US8450711B2
Hewlett Packard · Memristor patent		 2013 Passive resistance-switching elements. Cannot make autonomous decisions at cell level. Y-code · novel
IBM · US11144718B2
IBM · Neuromorphic architecture		 2021 Network-level adaptation. Still requires external controller running conventional instruction loop. A-code · background
Univ. Michigan · US9111613B2
Mazumder & Ebong · Adaptive resistive memory read/write		 2015 Two-pulse adaptive method to determine logic state of memristor cells by measuring resistance change. Memory read/write protocol — no clock gating, no processor wake-up, no autonomous hardware decision chain. A-code · background

Wang et al. and HP received Y-category codes — closest prior art, considered in combination. IBM and University of Michigan received A-category codes — relevant background, not directly blocking. None of the four references achieved autonomous decision-making at the local cell level in standard CMOS. The RPU achieved it in 2,960 gates of synthesizable SystemVerilog, silicon-proven on TSMC 65nm and SkyWater SKY130.

The examiner found no single reference that anticipated the architecture.
Novelty and inventive step were not contradicted by any prior art found.
VI What we license

We operate a dual-licence model. Research and academic use is free — clone the repository, run the testbench, verify every result. For commercial use, a written licence is required.

Research & Academic
Free. Clone the RTL from GitHub. Run the simulation testbench and post-synthesis testbench. Verify every published result independently. No permission required.
Commercial Licence
Required for SoC integration, tape-out, and product deployment. Covers the RTL, C-HAL driver, ASIC PPA reports, and direct engineering support. Priced against the value we save you.
Evaluation
Free, time-limited. Run the RPU on your own architecture, your own sensor data, your own benchmarks. If it does not outperform your current implementation, we do not invoice.
Integration Support
Co-design consulting available for complex SoC environments. Direct access to the architecture team. Available alongside any commercial licence.

We will always ask for less than the value we save you. That is not a marketing line — it is the only pricing model that makes sense for a technology whose entire value is in what it eliminates.