RPU Microelectronics · IP Licensing

What We License
and How It Is Protected

Every always-on system first asks: has anything changed?
The RPU answers in hardware, before any computation starts.

We are a hardware IP company. We license one primitive: an adaptive rate-of-change comparator with memory, which decides when a signal has really changed with no CPU in the decision path. It is patent pending.

PCT/IB2026/053070 Patent pending Priority: TR 2025/012696 · 4 September 2025 PCT filed: 27 March 2026
I One company. One principle.

RPU Microelectronics is an IP licensing company. We do not build general-purpose chips or sell processor cores. Our work rests on one decision rule: when the rate of change of a state crosses a threshold, reconfigure; otherwise stay idle. The decision is taken inside the cell, with no program counter, controller or software in between.

The RPU is the first product built on that rule. It sits behind a sensor ADC, measures how fast the signal changes, adapts its threshold to the noise floor, and decides two clock cycles after each sample. It has been synthesized in TSMC 65nm and SkyWater SKY130 and tested on an FPGA board inside a RISC-V system. Tape-out is the next step.

A primitive, not a single block.
One RTL source, configured by parameters,
answering more than one "when" question.
II What changes. What does not.

The most common question from integration engineers is: will this force us to redesign our system? No. The RPU is a side-band peripheral. It reads your sample stream in parallel with your existing data path and drives a standard interrupt.

What changes
When your processor wakes: on a real change, decided two clocks after the sample
How often events can wake it: capped by a wake budget
What you know about your sensors: faults reported on a separate line
What does not change
Your sensor interface and data path
Your existing IP blocks
Your bus topology and interconnect
Your application logic

The block has no bus-master or memory-write path. Disconnect its wake line and your system behaves as it did before.

III The technology and the principle behind it

The delivered core keeps the last N samples in a ring buffer split into two halves, computes the absolute difference of their means with two running sums, and compares it with a threshold that adapts to the noise within set bounds. An event shell around it turns decisions into interrupts, caps the event rate and reports sensor faults, without ever writing the core's metric or threshold; a core option gates alarms by the shape of the change.

The same rule repeats at other scales. In front of a sensor, a processor or an accelerator today; in proposals, across arrays of cells under a policy engine. Nor is it tied to CMOS: a long-term research route, the Reflexive Processing Cell, would let material physics, such as the insulator-to-metal transition of vanadium dioxide, perform the threshold itself. That route is research, not a product.

IV Patent status

Our international application, PCT/IB2026/053070, was filed on 27 March 2026 and claims priority from Turkish application TR 2025/012696 of 4 September 2025. It is pending. No patent has been granted yet, and the final scope of protection will be decided in examination, country by country.

The filings describe the decision principle, the decision chain from temporal metric to physical action, the delivered implementation, the sensor-health side-band and the wider family of configurations. We do not describe pending claims as granted rights, and we do not ask a licensee to rely on them as if they were.

V Prior art cited in the search report

The search report issued by TÜRKPATENT for TR 2025/012696 cites four documents. In a search report, category Y marks a document that is relevant to inventive step when combined with another document, and category A marks general background.

Reference Year Approach Category
Wang et al.
Nature Communications · Cambridge, Beihang, UCL
 2024 Memristor-based adaptive neuromorphic perception, coordinated through an external control platform. Y
HP · US8450711B2
Hewlett Packard · memristor patent
 2013 Resistive switching element that retains past electrical stimuli. Y
IBM · US11144718B2
IBM · neuromorphic architecture
 2021 Adaptation at network level. A
Univ. Michigan · US9111613B2
Mazumder & Ebong · adaptive resistive memory read/write
 2015 Two-pulse adaptive method to read the state of memristor cells. A

The full report is public and can be downloaded below. The RPU differs from these approaches in where and how the decision is made: one decision rule, in standard CMOS logic, inside the block, with no controller or software in the path. Whether that difference is patentable is for the examiners to decide.

VI What we license

We operate a dual model. Research and academic use is free: clone the reference RTL, run the testbenches, check our results. Commercial use requires a written licence.

Research & Academic
Free. Reference RTL, simulation testbench and post-synthesis testbench on GitHub. No permission needed for research.
Commercial Licence
Required for SoC integration, tape-out and products. Covers the delivered RTL and event shell, calibration tool, ASIC PPA reports and engineering support. The RTL is delivered as readable SystemVerilog, not an encrypted netlist, so functions you do not use are removed from the source.
Evaluation
Free for 30 days, under NDA: core and system kits for a Nexys A7 board, with acceptance scripts and challenge tests. If it does not earn its place in your system, you owe nothing.
Pilot & Integration Support
We tune a profile on your recordings, freeze it, and report results on held-out data next to a comparator tuned on the same data. Co-design support for complex SoCs.

We will always ask for less than the value the RPU creates for you. For a block whose value lies in the computation it makes unnecessary, that is the only pricing model that makes sense.